This invention relates to a computer system comprising a great number of arithmetic processors, and more particularly, to a clock controlling unit for controlling supply of a clock signal in the computer system to the arithmetic processors.
A computer system generally comprises first through K-th arithmetic processors, where K represents a positive integer which is not less than two. The computer system further comprises a control section and a clock generator section. The control section has a plurality of connection ports to which the arithmetic processors are connected. The clock generator section generates a clock signal to supply the clock signal to the arithmetic processors and the control section so as to put the computer system into operation.
The control section controls the arithmetic processors so that the arithmetic processors can individually access a main memory unit which is connected to the control section. The arithmetic processors carry out communication with one another under the control of the control section.
A conventional clock generator section comprises a clock controlling unit for controlling supply of the clock signal to the arithmetic processors. It will be assumed that a fault occurs in a k-th arithmetic processor, where k represents one of 1 through K. The k-th arithmetic processor generates a fault signal to supply the clock controlling unit with the fault signal. The clock controlling unit stops supply of the clock signal to the k-th arithmetic processor in response to the fault signal. As a result, the k-th arithmetic processor is put out of operation.
The control section has the connection ports of a predetermined number. When the computer system comprises a great number of arithmetic processors in the case of a super computer system, namely, when the number of the arithmetic processors is greater than the predetermined number, it is impossible to connect the arithmetic processors to the connection ports of the control section, respectively.
In order to increase the number of the arithmetic processors which are connected to the connection ports, it is desirable to connect the first through the K-th arithmetic processors in series to one of the connection ports. The first arithmetic processor is directly connected to the one connection port as a nearest arithmetic processor. The K-th arithmetic processor is located as a farthest arithmetic processor relative to the control section. In case where the arithmetic processors are connected in series, the clock controlling unit must stop supply of the clock signal not only to the k-th arithmetic processor but also to the (k+1)-th through the K-th arithmetic processors. This is because the k-th through the K-th arithmetic processors must be put out of operation when a fault occurs in the k-th arithmetic processor.
However, the clock controlling unit of the conventional clock generator section can not stop supply of the clock signal to the (k+1)-th through the K-th arithmetic processors when supply of the clock signal to the k-th arithmetic processor is stopped. This means that the first through the K-th arithmetic processors can not be connected in series to one of the connection ports when use is made of the clock controlling unit of the conventional clock generator section. Therefore, it is difficult to increase the number of the arithmetic processors as desired.